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About this paper
Dejanira Araiza-Illan, Kerstin Eder, Arthur Richards
Researchers at the University of Bristol devised a methodology for the deductive formal verification of control system properties directly within Simulink models. Their approach integrates custom assertion blocks for dual simulation and formal specification, an automated translator to the Why3 logic language, and subsequent verification using SMT solvers, validating system stability for a first-order discrete system.
Key insights
- The proposed methodology enables a
- dual-purpose
- specification approach where the same assertions used for dynamic simulation can be leveraged for rigorous formal proofs, increasing design confidence.
- Formal verification can be applied directly to Simulink models at the block diagram level, integrating verification earlier in the design cycle and avoiding issues arising from translation to other formalisms or generated code.
- The use of SMT solvers within the Why3 framework allows for effective handling of real-valued signals and continuous system dynamics, overcoming a limitation of some model-checking techniques.
Summary by alphaXiv.
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