Reproduce “Weighted p-bits for FPGA implementation of probabilistic circuits” on OpenResearch
Turn your favorite coding agents into research agents that review literature, develop hypotheses, and run experiments.
Universal app for Apple silicon and Intel. Requires macOS 11 or later.
About this paper
Ahmed Zeeshan Pervaiz, Brian M. Sutton, Lakshmi Anirudh Ghantasala, Kerem Y. Camsari
The authors present a tiled FPGA system of weighted p-bits that samples inputs compatible with clamped logic outputs. Each p-bit combines connection weights with stochastic updates. They construct an invertible full adder using 5 p-bits rather than 14; a 32-bit adder samples S-A-B=0 in about 20% of 10^5 trials. The subset-sum test favors the correct target on an easy instance.
Summary by alphaXiv.
Tip: change arxiv.org to autoarxiv.org in any arXiv abstract link to open the paper here.