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About this paper
Johannes de Fine Licht, Maciej Besta, Simon Meierhans, Torsten Hoefler
Researchers at ETH Zurich's Scalable Parallel Computing Lab systematically define and categorize hardware-aware optimizing transformations for High-Level Synthesis (HLS) codes. Applying these transformations to HPC kernels on FPGAs yields substantial performance gains, with observed speedups reaching up to 29,950x for matrix multiplication compared to naive HLS implementations.
Key insights
- Achieving a perfect initiation interval (I=1) through pipelining transformations, such as accumulation interleaving and delay buffering, is the crucial first step for HLS code optimization.
- Vertical unrolling emerges as a potent method for extracting parallelism on FPGAs, leveraging temporal locality and on-chip memory rather than solely relying on external memory bandwidth.
- Explicit dataflow partitioning of functionality into multiple processing elements linked by streaming channels enhances modularity, reduces compilation time, and mitigates routing challenges for complex designs.
Summary by alphaXiv.
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