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About this paper
Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric
ARM Inc. researchers developed a systematic methodology for designing and optimizing standard cell libraries tailored for the 7nm ASAP7 PDK. This approach characterized how different standard cell architectures and library richness impact power, performance, and area (PPA) on the Arm Cortex-M0 processor, achieving timing closure at 1.0 GHz with the 9-track alpha library.
Key insights
- 9-track standard cell architectures consistently offer superior performance, enabling higher frequencies (e.g., 1.0 GHz) at the cost of increased power and area, while 7.5-track architectures are suitable for area/power-constrained designs.
- Richer standard cell libraries provide significantly improved overall PPA and design closure for high-frequency targets by offering greater flexibility to synthesis tools compared to minimum libraries.
- Evaluating standard cell libraries with a full synthesis flow is crucial to capture block-level Design Technology Co-Optimization (DTCO) trade-offs, as simple cell-level metrics alone do not fully reflect system-level impact.
Summary by alphaXiv.
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