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About this paper
Md Aamir Raihan, Negar Goli, Tor Aamodt
Researchers at the University of British Columbia reverse-engineered NVIDIA's Tensor Core architecture in Volta and Turing GPUs, developing a microarchitectural model that was integrated into the GPGPU-Sim simulator. This enhanced simulator achieved a 99.6% IPC correlation with real hardware for Tensor Core-enabled workloads and provided detailed insights into their operation and performance.
Key insights
- Operand matrix element mapping to threads and register usage differs between Volta and Turing architectures; Volta exhibits data redundancy, enabling independent processing by 'octets'.
- PTX `wmma.load`/`wmma.store` instructions map to standard SASS load/store, indicating direct register file access, while `wmma.mma` is implemented via the new `HMMA` SASS instruction.
- The proposed Volta microarchitecture suggests two Tensor Cores per warp, each handling two octets and equipped with sixteen pipelined FP16 Four-Element Dot-Product units.
Summary by alphaXiv.
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