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About this paper
Abdelrahman Hosny, Soheil Hashemi, Mohamed Shalan, Sherief Reda
A deep reinforcement learning framework, DRiLLS, autonomously generates logic synthesis optimization flows for digital circuits. This approach minimizes design area while adhering to specified timing constraints, achieving an average area improvement of 13.19% and consistently meeting delay targets on benchmark designs.
Key insights
- Deep reinforcement learning agents can effectively learn to compose variable-length optimization flows for complex, combinatorial problems in hardware design, eliminating the need for human experts.
- A carefully designed multi-objective reward function is crucial for guiding RL agents to achieve desired trade-offs, such as minimizing area while consistently satisfying strict delay constraints.
- Normalized AIG characteristics serve as a robust and generalizable state representation, enabling the RL agent to adapt and optimize diverse circuit designs without specialized training data per circuit.
Summary by alphaXiv.
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