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About this paper
Albert Reuther, Peter Michaleas, Michael Jones, Vijay Gadepally, Siddharth Samsi, Jeremy Kepner
A comprehensive survey of publicly announced machine learning accelerators systematically collects and visualizes their peak performance and power consumption, identifying key trends and aiding hardware selection for diverse applications. The work from MIT Lincoln Laboratory Supercomputing Center updates previous efforts by providing a detailed catalog and analysis of hundreds of devices, highlighting architectural diversity and power-efficiency improvements in the rapidly evolving AI hardware landscape.
Key insights
- A rapid increase in new accelerator chips and systems is observed across all application categories, indicating an intensely competitive and innovative market.
- There is an increasing diversity of underlying architectures beyond traditional CPUs and GPUs, including dataflow engines, neuromorphic designs, and analog/photonic processing.
- A clear distinction in power demands persists, with training requiring significantly higher power (typically >100W) compared to inference, which often leverages lower precision for efficiency.
Summary by alphaXiv.
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