Reproduce “SME: ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit Sparsity of Neural Network” on OpenResearch
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About this paper
Fangxin Liu, Wenbo Zhao, Yilong Zhao, Zongwu Wang, Tao Yang, Zhezhi He, Naifeng Jing, Xiaoyao Liang and 1 more
The SME framework introduces an algorithm-hardware co-design for ReRAM-based accelerators, effectively exploiting fine-grained bit-level sparsity in neural networks by decoupling the crossbar structure from sparse bit patterns. This approach yields up to an 8.7x reduction in ReRAM crossbar usage and a 2.3x improvement in energy efficiency with minimal accuracy loss (≤ 0.3%).
Key insights
- Strategic quantization that concentrates '1's within a specific bit-region systematically accumulates '0's outside this region, creating exploitable bit-level sparsity.
- Mapping weights by individual bit positions across distinct crossbars (bit-slicing) effectively decouples the structural coupling, allowing entire highly-sparse crossbars to be saved or skipped.
- Compensating for bit-shifts by modifying the input stream rather than the output stream for squeezed-out rows significantly reduces hardware overheads related to index storage and complex control logic.
Summary by alphaXiv.
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