Reproduce “A 120dB Programmable-Range On-Chip Pulse Generator for Characterizing Ferroelectric Devices” on OpenResearch
Turn your favorite coding agents into research agents that review literature, develop hypotheses, and run experiments.
Universal app for Apple silicon and Intel. Requires macOS 11 or later.
About this paper
Shyam Narayanan, Erika Covi, Viktor Havel, Charlotte Frenkel, Suzanne Lancaster, Quang Duong, Stefan Slesazeck, Thomas Mikolajick and 2 more
A 180 nm CMOS on-chip pulse generator was developed to enable accurate characterization of ferroelectric devices by mitigating external parasitic loads. This integrated solution provides a 120 dB programmable range, generating pulse widths from 10 ns to 10 ms, with an achieved pulse width error of less than ±2.5% after calibration.
Key insights
- Generating a ramp voltage through controlled capacitor discharge provides a robust mechanism for creating highly programmable pulse widths across many orders of magnitude.
- On-chip calibration, particularly using a programmable capacitor array (C_DAC), is critical for counteracting process variations and achieving high pulse width accuracy in fabricated circuits.
- Incorporating hysteresis into the comparator design is essential for preventing false triggering from noise on the ramp voltage, ensuring stable and reliable pulse generation across a wide range of settings.
Summary by alphaXiv.
Tip: change arxiv.org to autoarxiv.org in any arXiv abstract link to open the paper here.