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About this paper
Vanessa R. C. Leite, Zhe Su, Adrian M. Whatley, Giacomo Indiveri
A hardware-software co-design approach, developed by the Institute of Neuroinformatics, minimized memory resource usage in multi-core neuromorphic processors through a hierarchical routing scheme and a hardware-aware placement algorithm inspired by small-world biological networks. This method demonstrated efficient neuron mapping, achieving reduced memory overhead and identifying optimal core sizes for specific network topologies.
Key insights
- Leveraging small-world network characteristics from biological brains can significantly optimize memory requirements for connectivity and routing in neuromorphic hardware.
- A hierarchical routing scheme, tailored to the decay of connection probability with distance, is effective in reducing memory overhead by allocating address bits proportional to connection specificity and range.
- The efficiency of mapping SNNs onto neuromorphic hardware, particularly memory overhead, is highly dependent on hardware parameters like core size and its interaction with the network topology.
Summary by alphaXiv.
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