Reproduce “A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design” on OpenResearch

About this paper

Matteo Perotti, Matheus Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini

Ara couples CVA6 to an open-source vector unit supporting the vast majority of RISC-V Vector Extension (RVV) 1.0. Compared with the earlier system, it uses a 16 KiB rather than 64 KiB vector register file, with die area of 0.81 rather than 0.98 mm² and performance of 10.4 rather than 9.8 DP-GFLOPS. These are post-layout results, not chip measurements.

Key insights

• The RVV 1.0 specification's fixed striping distance (SLEN=VLEN) and flexible mask register layout necessitate complex data movement (shuffle/deshuffle) and dedicated mask handling units in lane-based architectures.
• The scalar core's memory subsystem characteristics and instruction issue rate significantly influence overall vector throughput, particularly for medium to short vectors, underscoring the importance of holistic scalar-vector system co-design.
• A fully RVV 1.0 compliant processor can achieve competitive PPA metrics and high FPU utilization, with its smaller Vector Register File (75% reduction) remaining sufficient for many compute-bound kernels.

Summary by alphaXiv.