Reproduce “HARFLOW3D: A Latency-Oriented 3D-CNN Accelerator Toolflow for HAR on FPGA Devices” on OpenResearch

About this paper

Petros Toupas, Alexander Montgomerie-Corcoran, Christos-Savvas Bouganis, Dimitrios Tzovaras

HARFLOW3D introduces the first automated toolflow for deploying 3D Convolutional Neural Networks for Human Action Recognition onto FPGAs, prioritizing execution latency. The system generates hardware designs that achieve competitive latency and DSP efficiency, outperforming some hand-tuned approaches by up to 5 times, while demonstrating comparable energy consumption per clip to high-end GPUs.

Key insights

• Runtime parameterization of hardware blocks is crucial for 3D CNN acceleration on FPGAs, leading to an 18.21x performance increase by eliminating padding and redundant operations.
• An automated, generic toolflow can generate FPGA designs for 3D CNNs that are competitive with, and often surpass, hand-tuned, model-specific approaches in terms of latency and DSP efficiency.
• FPGAs offer compelling energy efficiency for 3D CNN inference, achieving comparable energy consumption per clip to high-end GPUs, making them suitable for power-constrained edge applications despite lower absolute throughput.

Summary by alphaXiv.