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About this paper
Samuel Riedel, Matheus Cavalcante, Renzo Andri, Luca Benini
MemPool is a scalable manycore architecture that extends a single, tightly coupled shared L1 memory cluster to 256 independently programmable RISC-V cores. Implemented in 22FDX technology, it runs at 600 MHz and achieves up to 229 GOPS at 180 GOPS/W, demonstrating high performance and energy efficiency for diverse parallel workloads.
Key insights
- A single, tightly coupled shared L1 memory cluster can scale to hundreds of cores by carefully designing a hierarchical interconnect and employing a hybrid addressing scheme to minimize remote accesses and contention.
- Optimizing the instruction path through hierarchical caches (L0 private, L1 shared per tile) with prefetching and energy-efficient designs is crucial for high core utilization and power savings.
- A distributed, modular DMA engine, integrated within the hierarchical AXI interconnect, can efficiently stream data from off-chip memory to a large shared L1 SPM without significantly interfering with core operations.
Summary by alphaXiv.
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