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About this paper
Ekansh Agrawal, Xiangyu Sam Xu
DEAP proposes a simulation-driven framework for Design Space Exploration (DSE) of multi-accelerator DNN systems for LLM inference, extending DSE to consider inter-chip communication and network topologies. The work demonstrates that intelligent inter-chip connectivity is critical for performance, with stochastic searches for optimal topologies often converging on 3D Torus-like configurations that minimize latency.
Key insights
- Extending Design Space Exploration (DSE) to multi-accelerator contexts, considering hardware topology and inter-chip communication, is crucial for efficient LLM deployment.
- The presence of inter-chip connections significantly reduces latency in multi-accelerator systems compared to configurations without direct inter-chip links.
- For optimal performance in multi-accelerator LLM inference, stochastic search can uncover superior, often 3D Torus-like, topologies by minimizing average communication distances, outperforming fixed standard topologies for larger chip counts.
Summary by alphaXiv.
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