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About this paper
Marta Andronic, George A. Constantinides
NeuraLUT embeds entire Multi-Layer Perceptrons (MLPs) with full floating-point precision and skip-connections inside FPGA Look-Up Tables (L-LUTs), creating functionally dense yet shallow hardware-level networks. This approach achieves significant reductions in inference latency and area-delay product compared to state-of-the-art FPGA acceleration methods on MNIST and jet substructure tagging datasets.
Key insights
- Embedding MLPs significantly enhances the functional expressivity of individual L-LUTs, allowing each to compute complex continuous piecewise linear functions with exponentially more regions than prior approaches.
- This 'hidden density' enables the design of neural networks that are deep at the software level but very shallow at the circuit level, directly reducing inference latency by requiring fewer clock cycles.
- Skip-connections, when integrated within the hidden sub-networks, improve training stability for deeper internal MLP structures without altering the hardware topology or adding physical latency.
Summary by alphaXiv.
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