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About this paper
Rassul Bairamkulov, Mingfei Yu, Giovanni De Micheli
A new technology mapping methodology is introduced for Rapid Single-Flux Quantum (RSFQ) arithmetic circuits, which integrates area-efficient T1 flip-flops (T1-FFs) with multiphase clocking. This approach reduces circuit area and path-balancing D-flip-flop count by an average of 6%, and up to 25% for adder circuits, accepting a typical 13% increase in logic depth.
Key insights
- T1 flip-flops (T1-FFs) offer significant area reduction potential for arithmetic functions in RSFQ circuits, even with their stringent input timing requirements.
- Multiphase clocking provides an effective mechanism to precisely control signal arrival times, crucial for integrating components like T1-FFs and reducing path-balancing DFFs.
- An automated design methodology can overcome the challenges of integrating complex, area-efficient logic cells and advanced clocking strategies into RSFQ circuits.
Summary by alphaXiv.
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