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About this paper
Ye Cai, Zonglin Yang, Liwei Ni, Biwei Xie, Xingquan Li
Researchers at Shenzhen University developed a parallel computing method for generating supergates in ASIC technology mapping, efficiently leveraging multi-core processors. This approach reduces supergate generation time by up to 4x and yields an average circuit delay reduction of 10.1% compared to a baseline without supergates, while also achieving area reductions in specific mapping scenarios.
Key insights
- A richer library of supergates significantly reduces circuit delay in ASIC mapping, underscoring their importance for performance optimization.
- The exponential complexity of supergate generation necessitates parallel computing to overcome the trade-off between result quality and runtime.
- Effective parallelization requires careful design of data structures and concurrency control mechanisms to handle massive candidate generation and shared resource access.
Summary by alphaXiv.
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