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About this paper
Ruiyang Ma, Yuxin Yang, Ziqian Liu, Jiaxi Zhang, Min Li, Junhua Huang, Guojie Luo
VerilogReader introduces a framework that integrates Large Language Models into the hardware verification process to automate test generation for Verilog designs. The system demonstrates that LLMs can effectively generate test inputs to achieve code coverage goals, significantly outperforming random testing on simple and medium-complexity designs by requiring fewer stimuli.
Key insights
- Presenting coverage information in an LLM-readable format with explicit 'TO BE COVERED' flags significantly improves the LLM's ability to generate effective tests.
- Providing a natural language design description enhances the LLM's understanding and test generation capabilities, while explicit 'Test Guidance' can have mixed results.
- A two-round prompting strategy, first for reasoning about uncovered code and then for test vector generation, guides the LLM to produce appropriate stimuli.
Summary by alphaXiv.
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