Reproduce “FPGA-based Distributed Union-Find Decoder for Surface Codes” on OpenResearch
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About this paper
Namitha Liyanage, Yue Wu, Siona Tagare, Lin Zhong
Helios distributes Union-Find decoding across FPGA processing elements, assigning one to each vertex in the surface-code decoding graph. On VCU129, time per measurement round fell as code distance increased from 3 to 21 under phenomenological noise at p=0.001. At distance 21, it was 11.5 ns per round, a measured trend over tested distances, not a guarantee of indefinite scaling.
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