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About this paper
Tom Peham, Ludwig Schmid, Lucas Berent, Markus Müller, Robert Wille
The authors present SAT/SMT-based and heuristic methods for automatically synthesizing state-preparation and verification circuits for CSS quantum error-correcting codes. Simulations show the expected distance-dependent logical-error suppression; selected circuits also reduce gate or ancilla costs relative to projective initialization or measuring all stabilizers, though the trade-offs depend on the code and hardware assumptions.
Key insights
- Preparation and verification can be optimized as distinct synthesis problems; exact solving can certify optimality for tractable instances, while heuristics generate circuits quickly for larger codes.
- Fewer gates or ancillas do not necessarily mean lower circuit depth or better overall performance; measurement weight, flag overhead, parallelism, idle errors, and post-selection acceptance all matter.
- The layered verification scheme is designed to retain distance-dependent error suppression by detecting errors arising from multiple faults, not only those propagated from preparation.
Summary by alphaXiv.
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