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About this paper
Ruhai Lin, Rui-Jie Zhu, Jason K. Eshraghian
Researchers at UC Santa Cruz developed a hardware-software co-design strategy that leverages algorithmic bottleneck layers in neural networks to significantly reduce inter-chip data transfer in distributed systems. Their method quantifies the trade-off between model accuracy and hardware data movement, achieving up to a 70% reduction in data transfer volume for ResNet-18 at higher bottleneck ratios while identifying optimal accuracy points for certain models.
Key insights
- There is a direct trade-off: increasing the bottleneck ratio (more channel reduction) generally decreases model accuracy but substantially reduces data transfer volume.
- Deeper neural network architectures (e.g., ResNet101, ResNet152) exhibit greater resilience to information loss from higher bottleneck ratios compared to shallower models.
- For certain models like ResNet34 and ResNet50, a moderate bottleneck ratio of 2 can surprisingly yield the highest classification accuracy, suggesting a sweet spot for representational efficiency.
Summary by alphaXiv.
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