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About this paper
Faaiq Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu
An M3D FPGA architecture integrates BEOL AOS transistors for configuration SRAMs and routing pass gates, achieving a 3.4x lower area-time squared product, 27% lower critical path latency, and 26% lower reconfigurable routing block power compared to conventional CMOS FPGAs.
Key insights
- Amorphous oxide semiconductor (AOS) transistors, compatible with BEOL processing, offer ultra-low leakage and enable smaller, lower static-power configuration memories programmable at logic-compatible voltages.
- Monolithic 3D integration allows for stacking configuration memories and routing elements directly above configurable logic blocks, leading to significant area reduction and shorter interconnects.
- Overdriving AOS pass gates in routing blocks can eliminate the need for power- and latency-intensive level-restorers, improving overall routing efficiency.
Summary by alphaXiv.
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