Reproduce “VeriThoughts: Enabling Automated Verilog Code Generation using Reasoning and Formal Verification” on OpenResearch
Turn your favorite coding agents into research agents that review literature, develop hypotheses, and run experiments.
Universal app for Apple silicon and Intel. Requires macOS 11 or later.
About this paper
Patrick Yubeaton, Andre Nakkab, Weihua Xiao, Luca Collini, Ramesh Karri, Chinmay Hegde, Siddharth Garg
Tip: change arxiv.org to autoarxiv.org in any arXiv abstract link to open the paper here.