Reproduce “VerilogLAVD: LLM-Aided Rule Generation for Vulnerability Detection in Verilog” on OpenResearch

About this paper

Xiang Long, Yingjie Xia, Xiyuan Chen, Li Kuang

VerilogLAVD establishes a framework for hardware vulnerability detection in Verilog by leveraging Large Language Models to generate validated, graph-based rules, achieving an F1-score of 0.57 and reducing rule primitive misuse to 10.10% on a custom dataset of 12 CWE types.

Key insights

• A hybrid approach that combines LLMs for high-level rule interpretation with precise graph-based static analysis effectively addresses LLM weaknesses in structural code understanding while leveraging their natural language capabilities.
• Implementing a robust, real-time rule validation mechanism is crucial for improving the reliability of LLM-generated structured outputs, significantly reducing errors like "hallucinations" and "API misuse."
• The VeriPG representation and its specialized executor enable efficient vulnerability detection, demonstrating insensitivity to irrelevant code sections and maintaining high performance on lengthy Verilog designs.

Summary by alphaXiv.