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About this paper
Henry Kao, Nikhil Sreekumar, Prabhdeep Singh Soni, Ali Sedaghati, Fang Su, Bryan Chan, Maziar Goudarzi, Reza Azimi
TRRIP introduces a software-hardware co-design for instruction caching that uses compiler-identified code "temperature" to guide a modified RRIP cache replacement policy. This approach, which integrates with existing OS page tables, yields a 3.9% geomean speedup and a 27.3% reduction in L2 instruction cache misses on PGO-optimized mobile workloads with negligible hardware overheads.
Key insights
- "Hot" instruction code, even after PGO, frequently exhibits high reuse distances, leading to premature eviction from L2 caches and persistent frontend stalls.
- Leveraging global, offline software intelligence (compiler-derived code temperature) via a lightweight OS-hardware interface (PTE bits) can effectively guide dynamic cache replacement decisions without significant overhead.
- Selective prioritization of hot and warm code, rather than all instruction lines, is crucial for optimal performance, as aggressive marking can lead to diminishing returns or performance degradation.
Summary by alphaXiv.
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