Reproduce “Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim” on OpenResearch

About this paper

Wajid Ali, Ayaz Akram, Deepak Shankar

A simulation-driven study utilizing VisualSim Architect evaluates chiplet-based architectures, demonstrating their performance and scalability advantages over monolithic designs. The research reveals that dedicated DRAM in chiplets reduces task completion latency, though increased core counts in multi-chiplet setups introduce slight latency increases and higher total power consumption, compensated by improved power efficiency per task.

Key insights

• Dedicated DRAM modules in chiplet architectures reduce memory contention and task completion latency, improving performance compared to shared memory in monolithic designs.
• Scaling core counts in chiplet systems enhances computational power but introduces increased inter-chiplet communication overhead, leading to marginal increases in overall latency.
• Chiplet architectures generally exhibit higher total power consumption due to inter-chiplet interconnects and additional active components, which can be offset by improved power efficiency per task for demanding workloads.

Summary by alphaXiv.