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About this paper
Giuseppe Chiari, Michele Piccoli, Davide Zoni
Researchers from Politecnico di Milano introduced OSIRIS, a scalable pipeline for generating large, physically accurate datasets for analog integrated circuit layout design, producing 87,100 DRC-clean and LVS-verified variants. This framework enabled an RL-based optimization method to achieve PEX scores over an order of magnitude smaller for some circuits and nearly 50% faster acquisition times, also demonstrating its utility in fine-tuning an LLM for capacitor layout generation.
Key insights
- Scalable dataset generation is crucial for enabling machine learning applications in the traditionally manual and expert-driven analog integrated circuit back-end design.
- Iterative, performance-driven design space exploration, facilitated by comprehensive post-layout feedback (e.g., PEX scores), can significantly improve the quality and efficiency of analog layouts compared to single-pass automation.
- Domain-specific, physically accurate datasets are essential for fine-tuning large language models or other ML techniques to achieve manufacturable and functionally correct physical layout generation.
Summary by alphaXiv.
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