Reproduce “TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-up Cluster Design with High Bandwidth Main Memory Link” on OpenResearch

About this paper

Yichao Zhang, Marco Bertuletti, Chi Zhang, Samuel Riedel, Diyou Shen, Bowen Wang, Alessandro Vanelli-Coralli, Luca Benini

TeraPool is a physically design-aware, 1024 RISC-V core cluster featuring a shared L1 memory and a hierarchical interconnect, demonstrating the feasibility of scaling up beyond traditional limits. It operates at up to 910 MHz and achieves 1.89 single precision TFLOP/s with up to 200 GFLOP/s/W efficiency in a 81.8 mm² die area using 12nm FinFET technology.

Key insights

• Hierarchical interconnects are essential for scaling shared-L1 memory clusters beyond 1000 cores, effectively managing physical complexity and achieving near-gigahertz frequencies.
• Strategic placement of pipeline registers and physically aware floorplanning are critical for routability and timing closure in large-scale integrated designs.
• Effective latency hiding through non-blocking loads, transaction tables, and double-buffering is key to sustaining high computational utilization across diverse memory access patterns.

Summary by alphaXiv.