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About this paper
Kanishka Gunawardana, Sanka Peeris, Kavishka Rambukwella, Thamish Wanduragala, Saadia Jameel, Roshan Ragel, Isuru Nawinne
Researchers developed SNAP-V, a RISC-V System-on-Chip featuring the Cerebra-H neuromorphic accelerator, designed for energy-efficient execution of small-scale Spiking Neural Networks. This platform achieves an intrinsic compute efficiency of 1.05 pJ per synaptic operation and identifies synaptic weight memory as consuming 95.97% of total power.
Key insights
- The core event-driven SNN computation and communication logic can achieve high energy efficiency (1.05 pJ/SOP for compute) when isolated from memory access overhead.
- The weight memory subsystem is the predominant power consumer in neuromorphic SoCs (95.97% of total power in Cerebra-H), highlighting its critical impact on overall system efficiency.
- A hierarchical Network-on-Chip (NoC) and clustered neuron organization significantly improve communication efficiency and operating frequency, achieving a 9.46-fold speedup over a shared bus architecture.
Summary by alphaXiv.
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