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About this paper
Yi Ren, Yukun Wang, Xiang Meng, Guoyao Cheng, Baokang Peng, Lining Zhang, Yibo Lin, Runsheng Wang and 1 more
CellE extends standard-cell libraries by mining reusable logic across equivalent forms of a mapped circuit. It builds an e-graph and applies selected Boolean rewrite rules before mining subcircuits and mapping with candidate cells. On EPFL’s 17-circuit FreePDK45 experiment, geometric-mean area reduction versus the original library was 15.41%, compared with TeMACLE’s 14.36%; results varied by circuit.
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