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About this paper
Júlia Orteu Aubach, Fabio Banchelli, Marc Clascà Ramírez, Marta Garcia-Gasulla
A heuristic-based methodology merges High-Performance Computing (HPC) execution traces from multiple runs, each collecting different hardware counter sets, to create synthetic enriched traces that extend hardware counter coverage at the burst level while preserving temporal fidelity. The approach successfully matches bursts across various application determinism levels, with instruction and floating-point counters showing high precision, while cache counters exhibit greater inherent variability.
Key insights
- The methodology effectively reconstructs rich, unified performance traces, overcoming hardware limitations without sacrificing temporal precision.
- Instruction and floating-point operation counters demonstrate high consistency and precision across merged traces, making them reliable for performance prediction.
- Cache hierarchy counters exhibit significant inherent measurement variability, regardless of application determinism, suggesting they are less suitable for burst-level performance prediction based on merged data.
Summary by alphaXiv.
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