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About this paper
Shafayat Mowla Anik, Yongchan Jung, Jeeho Ryoo, Byeong Kil Lee
Researchers from the University of Colorado at Colorado Springs and Fairleigh Dickinson University characterize "dead-entry TLB misses" in GPU microarchitectures, where recently evicted translations are immediately re-accessed. They introduce a lightweight hardware mechanism, DEPOT, which prevents these redundant re-walks and improves performance by up to 72% for specific interference-driven workloads, while offering additive benefits with existing prefetching techniques.
Key insights
- Dead-entry misses constitute over 98% of L2 TLB misses in TLB-sensitive GPU workloads, but their performance impact is highly dependent on the underlying memory access patterns and MSHR merging behavior.
- GPU workloads can be categorized into 'interference-driven' (showing bursty MSHR occupancy and high sensitivity to dead-entry re-walks) and 'capacity-driven' (showing flat MSHR occupancy, primarily limited by TLB capacity).
- A simple, low-overhead eviction-history protection mechanism can effectively mitigate performance bottlenecks for interference-driven workloads and is largely orthogonal to access-pattern prediction methods.
Summary by alphaXiv.
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