Reproduce “BigPower: Hierarchical Source-Level Module Power Estimation for CPUs with Large Language Models” on OpenResearch

About this paper

Honghua Zhu, Chunjie Luo, Jianfeng Zhan

BigPower, a system developed at the Chinese Academy of Sciences, employs large language models to perform hierarchical source-level module power estimation for CPUs, achieving an overall average Mean Absolute Percentage Error (MAPE) of 15.64% and an R^2 of 0.94 without requiring dynamic simulation. The approach provides fine-grained power breakdowns and sensitivity analysis for microarchitectural changes directly from design source code.

Key insights

• Large Language Models can effectively learn and generalize from heterogeneous textual representations of hardware designs (RTL code, structural metadata) to perform quantitative power estimation, bridging the gap between high-level design descriptions and low-level power characteristics.
• Strategic data representation, including explicit encoding of microarchitecture configurations, hierarchical structure, and module connectivity alongside RTL code, is crucial for enabling LLMs to understand the complex context required for accurate, fine-grained hardware power prediction.
• A multi-pronged prediction strategy, combining hierarchical inference, ensemble methods, and numerical stabilization techniques, is essential to achieve robust and reliable quantitative outputs from LLMs in complex engineering domains like CPU power estimation.

Summary by alphaXiv.