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About this paper
Jing Jin, Robert Chu, Ning Yan, Masood S. Mortazavi
LLM4RTL uses small language models to generate Verilog from tabular specifications. Scripts infer logical relationships from tables, waveforms, or Karnaugh maps and provide them to models for code generation. Tools raise PASS@1 on VerilogEval-human from 0.5279 to 0.6003 without retraining; on Circuit2, successes rise from 0 of 20 to 20 of 20. The tools target simple circuit modules, and gains vary across tasks.
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