Reproduce “Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA” on OpenResearch
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About this paper
Muhammad Usman, Yousef Sadegheih, Dorit Merhof
An FPGA-based accelerator for U-Net convolutional layers, integrating a novel merged multiply-add unit with Most-Significant-Digit-First digit-serial arithmetic, achieves 15.14 GOPS/W, demonstrating over 7x higher energy efficiency than CPU and 2.7x higher than GPU for U-Net inference.
Key insights
- Fusing digit-serial multiplication and accumulation into a single Most-Significant-Digit-First (MSDF) unit effectively mitigates the problem of accumulating initial delays in cascaded operations.
- Utilizing redundant number systems like Signed Digit (SD) radix-2 in the merged multiply-add unit supports early output generation and partial result correction, enhancing digit-serial arithmetic efficiency.
- Parallelizing multiple Kernel Processing Blocks (KPBs), each integrating several MMA units, allows for high-throughput processing of convolutional layers by handling multiple spatial input depths concurrently.
Summary by alphaXiv.
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