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About this paper
Tushar Garg, Andrew Boutros
Researchers from Meta Platforms, Inc. and the University of Waterloo developed an open-source tool for automatically generating efficient, vendor-agnostic hardware parsers for FPGAs from high-level specifications. The tool achieves up to 97% fewer LUTs and 226% higher operating frequency for Ethernet parsing compared to prior work, while also demonstrating versatility in generating hardware for Snort rule matching.
Key insights
- A modular architecture with a generic intermediate representation (PIR) enables versatile hardware parser generation across diverse application domains and high-level input languages without modifying the core RTL generation logic.
- Hierarchical decomposition of complex pattern matching problems significantly reduces logic resource utilization (up to 8x) and improves operating frequency by exposing common substrings for optimization by synthesis tools.
- Custom symbolic tokens with configurable logical predicates allow automated hardware parsers to express sophisticated logic beyond simple equality checks, broadening their applicability to complex tasks like network intrusion detection.
Summary by alphaXiv.
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