Reproduce “A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node” on OpenResearch
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About this paper
Po-Chuan Wang, Dongwon Jang, Eknath Sarkar, Alexei Svizhenko, Md. Nahid Haque Shazon, Piyush Kumar, Suman Datta, Azad Naeemi
The authors model a 2 nm SRAM that keeps its silicon-nanosheet latch in front-end-of-line and moves double-gate IGO access transistors into back-end-of-line, with shared bitline-side contacts. In a simulated 128-by-256 subarray, write delay is 42.2% lower and average read/write energy-delay product 9.7% lower than Si-HD; cell area is 25% below Si-HP. These are simulation results, not a fabricated SRAM.
Summary by alphaXiv.
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