Reproduce “Catscan: Visualizing Pipelines of CPU Performance Simulation” on OpenResearch
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About this paper
Aaron Lindsay, Nicholas Kelly, Scott Witscher, Mahesh Madhav
The authors present Catscan, a CPU debugging system that preserves links among trace events, transactions, and parent-child relationships. Its resource and transaction views let architects highlight activity and follow symptoms across instructions and microarchitectural events. In an industrial branch-misprediction example, tracing a flush revealed dropped training events for the branch’s PC; fixing the logic increased prediction accuracy, without a quantified gain or controlled evaluation.
Summary by alphaXiv.
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