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About this paper
Martin Langhammer, Bogdan Pasca, Gregg Baeckler
The authors tailor a RISC-V processor’s instruction format and hardware to an application, allowing synthesis to remove logic for instructions. Expanded instructions and software-inserted NOPs mean its binary is not a generic RISC-V executable. On a 200-element increasing-input Quicksort, it reports 170 ALMs and 1,310 μs versus Nios V/c’s 336 ALMs and 2,578 μs; this benchmark does not isolate specialization.
Summary by alphaXiv.
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