Reproduce “TileDRAM: Compiler-Controlled Tile-to-DRAM Layouts for 3D DRAM GPGPUs” on OpenResearch
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About this paper
Guangyuan Xu, Lanxuan Zhang, Ziyang Li, Zhaoshi Li, Yajun Ha
TileDRAM lets the compiler choose placement rules for recurring operand-tile access patterns in matrix multiplication. Compiler-generated address arithmetic improves DRAM row reuse without changing the controller’s address mapping. In simulator replay of 108 MoE feed-forward cases, request-weighted row conflicts fall from 75.7% to 15.2%, with 1.77× geometric-mean cycle speedup. Results cover tiled matrix multiplication on one compute-unit/stack pair, not physical DRAM validation.
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