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About this paper
Shintaro Yoshizawa
OCS treats inter-pod wiring as an optical-circuit allocation balancing iteration critical-path cost against divergence from a uniform reference under pod port limits. Its inverse-temperature parameter controls this tradeoff, while a GLR–CUSUM detector guides reconfiguration as synthetic workloads change. In synthetic tests, adaptive wiring reduced iteration time from 2.204 seconds to 1.384 seconds; these results do not establish production performance.
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