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About this paper
Saeid Rajabi, Aly Moussa, Vishal Saxena, Chengmo Yang, Satwik Patnaik
AnalogPortBench tests whether LLMs can port analog circuits across transistor processes while preserving specifications. It evaluates netlists through rule checks and simulation, including tasks requiring topology changes or an INFEASIBLE response. In one telescopic-amplifier task, Opus 5.5 replaced a failing stack with a two-stage Miller amplifier. The benchmark covers 54 tasks, including four infeasible cases limited to specified G1 circuits.
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