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About this paper
Nicholas Kovacs, Hao Zheng
The authors model an RV32I processor in C++ with explicit pipeline state, communication, and hazard rules, leaving HLS to schedule computations within that architecture. Four byte lanes remove the dependent read–merge–write for subword stores: before the trap fix, cycles fell from 1,684,686 to 842,339, while suite time improved 34% as maximum frequency dropped. Results cover the processor family and fixed-latency on-chip memory.
Summary by alphaXiv.
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