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About this paper
Jacky Wong, Jacob Alexandrou, Yinting Huang, Luke Panayi, Lev Mukhanov, Sam Ainsworth, Paul Kelly
Caerus learns memory-access patterns across instructions and filters offsets using per-instruction accuracy. In trace-driven ChampSim simulations of SPECspeed 2017, it achieves 8.3% geomean speedup, versus 6.1% for Berti, with 4.7% excess DRAM traffic compared with 20% for MLOP. Its hardware state is 2.86 KiB, but it does not lead on every workload.
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