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About this paper
Scott Smith, Lukas Zscherpel, Alyssa Huang, Marissa Lanz, Deming Chen
Naviq simulates FPGA-SoC systems that combine custom accelerators with network-on-chip, processor, and memory models. It replaces much of the platform infrastructure with cycle-level software models while integrating user SystemVerilog, enabling full-system studies. Against Vivado’s RTL NoC model, category-average accuracy is at least 97.6% for latency and 99.9% for bandwidth, with 81×–182× runtime speedups; results are tuned to AMD Versal-class systems.
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