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About this paper
Mehdi Safarpour
The authors present a reconfigurable accelerator that switches the same multiply-accumulate units between systolic and tensor-style execution per operation. The shared array reduces simulated wireless matrix-multiplication latency by 2.15–7.52× versus systolic execution. MobileNet achieves 1.65× speedup with 1.21% extra SRAM accesses. Both modes share the systolic-bandwidth memory interface; results are simulation and synthesis estimates, not deployed-chip application measurements.
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