Reproduce “AutoC2V: Synthesis-Guided LLM Training for QoR-Optimized C++-to-Verilog Generation” on OpenResearch
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About this paper
Guanqi Lyu, Fei Zhao, Zhaojun Lu, Jiaji He, Yongqiang Lyu
AutoC2V trains a model to generate Verilog RTL directly from C++ for latency or resource objectives, using 34,078 synthesis-derived examples from 201 regions. Supervised fine-tuning is followed by GRPO, which rewards functionally passing candidates with predicted hardware quality. On 24 common resource-objective kernels, its mean normalized score was 0.6030 versus 0.5195 for LLM-DSE, under the study’s evaluation setup and weights.
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